Independent at-home verification of ICs

theruran

I just wanted to start a thread about @stman's ideas for independent verification of an IC. Basically, how can we be sure, even if we have the complete blueprints of an IC design, that the physical chip in front of us accurately and faithfully implements the design? This is similar to the problem of verifying whether a software binary is an accurate transformation of the corresponding software source code. A lot of people, even FOSS engineers, ignore this problem, but it has far-reaching implications for security, trust and freedom. Namely, backdoors can be inserted without the user's knowledge. With the Trusting Trust attack, it is impossible without double-compilation with verified-trusted compilers to be sure that the compiler does not insert Trojans in software binaries including of the compiler itself.

@stman was conceptualizing a technique using the Optical Processing Unit from a standard Bluray drive to scan the surface of an IC, in order to create a detailed image without the use of an electron microscope or X-ray machine. The image can then be analyzed and compared to the blueprints for at least a surface-level verification. Perhaps an AI technique can be used to characterize the images to assist the human in verification.

Would love to see some more discussion on these ideas! One idea we had much earlier was attaching LEDs to chips to visualize their states. And another is to dispose of the industry technique of encasing the IC in opaque material, instead preferring some transparent medium so a visual inspection can easily discern if there are extra chips inside the carrier. We must keep in mind that the industry was born of capitalism and heavy military funding and top secret uses. We must envision computing with an anarcho-socialist mindset, one that champions operators and protects their human rights, while minimizing externalities.

stman

Definition of "Free Integrated Circuits" :

It's the same meaning as for Free Software, but for Integrated Circuits / Electronic components.

It is not to be confused with "Free Hardware" that usually refers to "Free PCB Boards" (The schematic of the board, and its processed, placed and routed equivalent PCB Layers) which are Free in terms of board schematic and routed PCB, but always made out of non-free electronic components. Indeed the wording "Free Hardware" is bad, because it tends to let users understand that the whole device hardware is free, while only its PCB is free, not all the components it is made of. This confusion is obviously serving cyber-imperialist goals of the Empire or competitors as it is greatly contributing to mask the "Free Integrated Circuit" problem and needs. "Free Hardware" is therefore a terminology with political and geopolitical fascist and imperialist bad consequences : It opens an avenue to the huge lie by omission that "Free Hardware" gives end-users full knowledge and control over its electronic devices, while it actually gives the user only a superficial, top level control over its electronic devices at PCB board level, not at integrated circuits levels.

That being said, creating truly fully free integrated circuits or electronic components in general is a way more complex task that the ones needed for free software. I propose to examine in details the different aspect of free software, and have a look at their equivalency for free integrated circuits :

TO DO : Insert a few paragraphs on free software main mandatory characteristics and their equivalency for free integrated circuits.

We can conclude from previous paragraphs that it is way more complex in terms of implementation to offer the same kind of freedom guarantees offered by Free Software :

Source code (VHDL) or schematic available to end-users for peer review and understanding how it works and how to use it and integrate it into designs.
Source code or schematic publish under a GPL licence or equivalent.
Free Software Tools available to compile the VHDL source code or process the schematics and generate the typon of each layer that will physically instantiate the targeted design IC, "the chip", and ensure & check that all those typons IC layers do implement exactly what was specified in the source code or schematic, and feed these typons to a fab so that the IC Chip can be manufactured. These typons for each IC layers are to be seen similarly as PCB layers for a PCB.
The need of a Free Standard Cells Library published under GPL or equivalent to instantiate each elementary Logic Gate for digital ICs.

These needs describe above are usually considered by the vast majority of Electronician and IC hackers as sufficient to characterize Free Integrated Circuits. But this is not the case, this is a lie by omission.

So what is missing in this usually accepted definition of Free Integrated Circuits ?

What is missing to offer all the same freedom guarantees as for Free Software is a low cost and simple process, for end-users, is :

The ability to simply, safely, non destructively, and as often as needed or desired open the Chip package (Some new packages that can be opened and close as many times as desired by end-users will need to be engineered) so that some low cost tools can later on verify the full integrity or partial integrity of the die it contains.
Verify the die means verifying that all the layers of the die that is embedded into the package do actually strictly correspond to the ones obtained by compiling the source code / processing the schematics to place and route each elementary logic cell and create the typons for each layer. In other word, the name of the game here is to check that the fab strictly used the same typons as those they were feed with to manufacture the device.
Verify that each logic gate is actually operational and working normaly (This is needed to mitigate dopant attacks, for example, and to ensure the IC is operational).
All this need to be doable "in situ" by the end-user himself, with a low cost apparatus that would act like a costly electronic microscope or X-Ray microscope able to see "nanoscale" details. And this is the hard part, because not only there is currently no specific "openable package" standardized, and these is no low cost technology commercialized to scan the die and its different layers like a costly electronic microscope can do, and automate the reconstitution of the full circuitry with all its layers and automatically compare those data to the original ones provided to the fab to manufacture the IC.

Free Integrated Circuits don't exist yet :

This is what can be concluded honestly from the definition above. There is strictly nothing allowing an end-user to check the die integrity of any integrated circuit, no apparatus exist to automate such task, and no "openable" package neither exist or have been standardized. This is clearly a fascist and cyber-imperialist political choice that has lead us to the current situation were we have, as end-users, absolutely no control over "in situ" integrity check of IC.

The best that can be done today :

In order to have an equivalent of Free Integrated Circuits or getting very close from that, we can (Ordered from the less secure but most easy to implement, to the most secure but less easy to implement) :

Use FPGA (There are still no Free FPGA) with free compilation, place and route toolchains, but there are NSA or equivalent backdoors within those FPGA ICs (We know how to mitigate them enough, but it brings a lot of useless additional complexity to the PCB designs). We have free compilation toolchains available (YOSYS) to compile, instantiate, place and route VHDL code, for FPGA or ASICs, but this is the best we can do.
Create ASICs with YOSYS and other free software synthesis tools, using a free Standard Logic Cell library like the one developped by LibreSilicon, but we can't trust the fab who is going to actually manufacture the IC and some backdoors could be inserted covertly by the fab. If no backdoor is inserted by the fab, then we almost have a free integrated circuit, but end-users still can't open the packages and check the full integrity of the circuit : The end-users is still forced to trust the supplier of the IC for being what it should really be. Then, we must understand that we can face post-manufacturing supply chain attacks : Even if the IC produced by the fab is clean and unmodified according to the original manufacturing files (typons) we given to the fab to produce the IC, some supply chain attack can still occure when the fab sends parcels containing these freshly produced IC to you : NSA TAO teams are used, like many other agencies, to intercept parcels, covertly open them, change their contant (Replace the clean ICs with backdoored ones they would have produced covertly). Another problem with ASICs is that if we want to make modifications, the ASIC IC produced become obsolete and must me trashed, they cannot be updated after manufacture. Still, when everything goes right, if the fab is not corrupted, and if we can prevent post-manufacturing supply chain attack for those IC transportation (Transporting them ourselves, physicaly, with our own trusted means, from the fab to the end-users), then we can say that we have free integrated circuit except that the end-users still can't check by themselves we were honest with them : It's still pretty a pretty interesting result, it's very close from full free integrated circuits, and it's much safer that current FPGAs that we know are backdoored.
Implement a design with good old discrete logic (TTL/CMOS) families like the 74xxx families or 4000 families. There are free tools based on YOSYS that can generate PCB Netlist for KiCad using those TTL/CMOS discrete logic gates families, allowing to further place and route them on a PCB from a VHDL source code : Here we can be sure there are no backdoors, if the synthesis tool can be trusted. The end-user can verify the PCB, the design, so here, we have a true operational equivalent of free integrated circuits. The drawback here is the size of the boards, some speed limitations of these discrete logic gates, and ultimately, the design cannot be modified easily when soldered on a PCB, still, it is possible to correct a few bugs the good old way with a few straps and so on.
Implement a design fully hardcoded design on a PCB with discrete logic gates families as above, but without using automated synthesis tools, doing everything manually, the good old way. For many small to medium complexity designs, it's really the best choice as there are no issues of trust with the free synthesis tool.
Doing the same but instead of using discrete logic gates families like those 74xxx or 4000 TTL/CMOS families, we can use discrete transistors. This is the safest, but boards can get rapidly huge, like the number of transistors needed, but it is still an option for small to some medium complexity designs. It can be done with free automated synthesis tools, or manually, the good old way.

Now, I think it is interesting to know that the several 3 last technics in the bullet list can be mixed. Some part of the design that really need the maximum level of transparency and guarantee against backdoors can use a different technics than less important parts. Still the last 3 items in the bullet list normally offer a level of trust almost perfect against backdoors insertion.

The current ICs that are the closest to the definition above are EPROMs thanks to their window that allow some microscopy on the die without destroying the IC, but it's just an optical examination of the die, and no test of each standard cells can be operated.

Crypto-Anarchist Roadmap to obtain truly free integrated circuits :

What we need now is to research and test some end-user simple technics with low apparatus to perform the two main operations that were missing to have those truly free integrated circuits :

Standardizing new custom "openable" packages for ICs and finding a fab to produce these new packages.
Researching a fully automated low cost apparatus to perform all the die integrity checking steps, by visual inspection and through micro probes to test each standard cell on the die.

Low cost apparatus for end-users IC full die integrity researches :

This is the biggest part of our collective efforts, and here, we can rely on previous great worl made by a few universities to create cheap nano scale microscopy technics.

The most promising research path is called HS-AFM (High-Speed Atomic Forces Microscopy) which can lead to nano-meter resolution microscopy scan and nano-meter electrical probing (When I say probing, it is the ability to pick up a signal on the die, or to inject a signal on the die at a specific location).

The most interesting work done for HS-AFM is using low cost CD/DVD drives OPU (Optical Pickup Units) (The "optical heads" of a standard CD/DVD player) combined with the precision of low cost cantilevers.

Combining two low cost technologies and technics has been done by a UK university :

https://research-information.bris.ac.uk/ws/portalfiles/portal/319227179/Final_PhD_Thesis_FRP.pdf

And it is giving very promising results : See page 90 of the PDF (Local number page number 60). On page 88 (58) you can see pictures of a cantilever "read" by the laser of an CD/DVD standard OPU.

A CD/DVD OPU costs about $30, and some cantilevers can be found for $300, which is still within the boundaries of what we can call "low cost".

A low cost cantilever supplier :

https://www.budgetsensors.com/standard-tapping-mode-afm-probes

The Tap300-G costs about $300 and would be perfect for our needs.

On the following link, you can read a good article on how OPU are also a loc cost apparatus promising research field for biohacking needs, which is not our primary goal, but still, it is interesting to have a look at this article :

https://pubs.acs.org/doi/pdf/10.1021/acssensors.8b00340

stman

End-User Low Cost apparatus for IC Integrity check : An improved approach.

In this new post, I will try to rapidly improve the previously methodology and technology for HS-AFM technic.

This second pass emphasis on the difficulties we will encounter with the HS-AFM presented above, and I will propose an improved pratical approach.

But let’s list the issues of the previous approach first :

If creating an HS-AFM device similar to what was presented in the Thesis of a british student ( https://research-information.bris.ac.uk/ws/portalfiles/portal/319227179/Final_PhD_Thesis_FRP.pdf ) is a good solution fitting our “low cost apparatus” criteria (Less than $1000 to duplicate the HS-AFM device), such device needs to be used into a ISO 5 Class 100 white room. Creating a white room ISO 5 Class 100 to embed the HS-ASM scanner is making solution only usable by qualified hackers into an hackerspace.
And the HS-ASM device scanner must be installed onto a very heavy metal table to ensure absolutely no or very low mechanical vibrations as possible (Like sounds vibrations or the vibrations we create when we simply walk into a room) means that special measures shall be taken to install the white room and the HS-AFM device. Again, if this is possible to do within a hackerspace, it is barely possible to implement at home for any user.
The HS-AFM scanning technic with cantilevers in non-tapping mode (The cantilever not touching physically the silicium die) to scan the surface of the die (HS-ASM process) is non destructive at all for the die, still, it means opening the IC package, process the scan, and then close it back. It is better to do such scan only once, to ensure no damage is done to the IC, even if in theory, there is absolutely no risk of damage, sound vibrations or other factors may mean that the cantilever could sometimes touch the die, and the number of times a full scan can be repeated on a die BEFORE it starts damaging the surface of the IC is still unknown to us, but we must anticipate the fact that the lesser HS-AFM scan is done for a given IC, the better.
Then, it must be added to the previous list that our goal is not only to identify and recognize each Standard Logic Cell on the die, we want also to detect any potential “dopant attack” or similar issue that could not be detected with a simple HS-AFM full scan of a die, even if such scan allow to identify each standard logic cell, each cell is still not tested individually. In order to test each cell (Meaning to inject a signal and read the output of a cell), we must use the HS-AFM to perform a second pass on the IC, where the cantilever will be used in taping mode (touching the die) to inject a signal and to read an output, like a probe. In order to do this, we just need a second cantilever that is gold metal coated (therefore electricaly conductive) so that it can be used as a probe.
Such second pass of our HS-AFM device onto the surface of the die with a conductive cantilever in taping mode is this time a process that will mecanicaly touch the die, and any repetitive touche can damage the layers of the die. This means that if it was preferable to do a single pass with the HS-AFM device in non tapping mode, when it is to do a second pass in taping mode to inject or read signals like a probe, then this process can be done only once not to damage the IC.

These limitations of the revolutionary HS-AFM technic presented in the thesis above were not taken into consideration in my first post.

After several discussions with some skilled hackers, it appeared that we must now think splitting our IC verification process into two steps :

A first step done only once for a given IC, in a hackerspace, with a low cost white room HS-AFM scanner, done into two passes, one to recognize and identify all the standard cells on the die, and another one in tapping mode with a conductive cantilever to act as an electrical probe in order to check each standard cell on the die to ensure the IC is 100% operational.
A second step, that each end user can do home indefinitely and as many time as needed to check his IC without performing all what is done in a hackerspace with the HS-AFM scanner, using an ultra low cost device (Less than $100), that don’t require white room or mechanical stability with no mechanical vibrations.

The present post is about this second step that end-user could reproduce at home as many times as needed for a given IC.

The proposed method and idea is to add a unique fingerprint to the die, a random one and a not reproducible one, easily checkable. Typically, a drop of transparent resin with tiny grains of glass melted into the resin, such fingerprint being glued to the same wafer than the IC wafer.

How would this work ?

After the IC integrity check done with the HS-AFM device into the hackerspace, this unique and not reproducible fingerprint, attached to the IC wafer, would be read thanks to a laser beam pointing at it, revealing a specific unique projected image thanks to the laser going through these random grains of glass within the resin drop attached to the die of the IC. Such process would not mean being obliged to open the package revealing the die where the standard cells are printed, but would only need to have access to the part of the die that contains the drop of resin.

In other word, during the IC verification process within the hackerspace with the HS-AFM scanner, we would also “read” the unique fingerprint associated to each IC with a laser. Such process is simple, and can be reproduced at home easily.

The concept here is to associate a unique random and not reproducible fingerprint to each IC, read this finger after the HS-AFM scanning process into the hackerspace, and then equip each user with an ultra low-cost device that can repeat the fingerprint reading at home.

This way, when a paranoid user at home wants to daily check that all his important IC were not replaced by backdoored ones, he would just need to read such unique fingerprint with a personal ultra low-cost device, mainly consisting of a simple laser diode beam hitting the drop of resin of each IC he wants to check. Checking the fingerprint being easy and can be done as many times as needed without damaging the IC. If the fingerprint is recognized, it means that the IC is the original one that was previously scanned with the HS-AFM device within the hackerspace.

Such strategy is the only way to keep end-user checking device ultra low-cost, and it’s also the only way to perform repetitive checking of given IC without damaging them.

Thank you for your attention. Comments and remark very welcome.

My next post, coming soon, will be about the improved HS-AFM scanning process in taping mode with a conductive cantilever used as an electrical probe. There are new constraints to add the the manufacturing process of an IC, including how a standard cell library shall be slightly modified, to ensure such process of the integrity check of an IC will be non destructive for the IC.